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Commit f0b705fd authored by Adrian's avatar Adrian

Update documentation, some info about scanpath

parent 971952dd
manual.pdf: overview.pdf
manual.pdf: manual.tex overview.pdf ../schematic/simple_overview/simple_overview.png
-pdflatex --interaction nonstopmode manual.tex
bibtex manual.aux
-pdflatex --interaction nonstopmode manual.tex
......
......@@ -92,25 +92,21 @@ Rev (commit id) & Date & Description \\ \hline
\newpage
\section{Introduction}
R5 is an 5 stage RISC-V\cite{risc-v} 32 bits processor. ISA supported by R5 is the base integer, RV32UI from 2.2 reference \cite{waterman_risc-v_2017} of RISC-V Foundation. All user instructions are supported except for \texttt{SYSTEM} instructions, since R5 does not have support for the privileged mode, and some instructions (FENCE.I, counters, and CSR) that will be implemented in the next version of the specification. The \texttt{fence} instruction is implemented as a \texttt{nop}, since R5 only has one hart\footnote{Hardware Thread}.
R5 is an 5 stage RISC-V\cite{risc-v} in-order 32 bits processor. ISA supported by R5 is the base integer, RV32UI from 2.2 reference \cite{waterman_risc-v_2017} of RISC-V Foundation. All user instructions are supported except for \texttt{SYSTEM} instructions, since R5 does not have support for the privileged mode, and some instructions (FENCE.I, counters, and CSR) that become extensions (no mandatory) in the next version of the specification. The \texttt{fence} instruction is implemented as a \texttt{nop}, since R5 only has one hart\footnote{Hardware Thread} and is in-order.
No exceptions nor interruptions are supported.
Extensions are not supported.
Here is an overview of our pipeline, a schematic with all the details can be found as annexe.
\begin{center}
\includegraphics[width=\textwidth]{"Untitled Diagram".png}
%TODO last update : 09/05
\includegraphics[width=\textwidth]{../schematic/simple_overview/simple_overview.png}
\end{center}
PC at reset is \texttt{0x08000000}.
We have tested our design with riscv-tests. All is synthesizable with Alliance. More details on how to use it can be found in \texttt{README.md} in the code
PC at reset is \texttt{0x08000000} and can be change in \texttt{Core/dec/dec.vhdl}.
We have tested our design with riscv-tests and on a \href{https://wiki.sipeed.com/en/tang/premier.html}{fpga}. All is synthesizable with \href{https://www-soc.lip6.fr/equipe-cian/logiciels/alliance/}{Alliance} or \href{www.clifford.at/yosys/}{Yosys} and can be place and route to produice layout with \href{https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/}{Coriolis}. More details on how to use it can be found in \texttt{README.md} in the code
% TODO global info
%Size use ; perf we got
% PC reset
% Some info about synthse, P&R etc...
\section{Interface of the core}
The R5 core has the following pads interfaces :
......@@ -143,7 +139,7 @@ We also have bypass from \texttt{EXE} output to \texttt{EXE} and \texttt{DEC} in
\section{IFETCH}
\texttt{IFETCH} consumes an address to fetch an instruction from \texttt{DEC} and get it from memory. \texttt{IFETCH} will forward the instruction and it's address (\texttt{PC}) to the \texttt{DEC} stage.
\section{DEC}
\texttt{DEC} is responsible for managing the flow of instructions (when either branch/jump or just go to pipeline) and decoding instructions to expend them to control \texttt{EXE}, \texttt{MEM} et \texttt{WB} stage. \texttt{DEC} also has a register bench with 32 registers (reg0 hardwire to 0) which have 2 read ports, 1 write port and 1 invalid port.
\texttt{DEC} is responsible for managing the flow of instructions (when either branch/jump, wait because of dependency with previous instructions or just go to pipeline) and decoding instructions to expend them to control \texttt{EXE}, \texttt{MEM} et \texttt{WB} stage. \texttt{DEC} also has a register bench with 32 registers (reg0 hardwire to 0) which have 2 read ports, 1 write port and 1 invalid port.
The \texttt{DEC} push to \texttt{IFETCH} address of instruction is required not just after the one that is currently decoded, but two in advance. With this we only have one instruction fetch lost on a branch/jump (but there is no delayed slot in RISC-V).
\subsection{How the next next PC is calculated}
......@@ -164,7 +160,6 @@ The comparator is able to handle signed and unsigned comparison between two 32 b
The comparator is logarithmic, here is an overview with an 8 bit example :
\begin{center}
\includegraphics[width=0.7\columnwidth]{comparatorpirouz.png}
%TODO last update : 12/05
\end{center}
Thanks to Pirouz Bazargan-Sabet for explanation.
......@@ -190,10 +185,10 @@ Then we do the same but with bit 3 of the shift amount, a shift of 8 positions,
As example this a logical shift left with a 4 bits input and a 2 bit shift amount:
\begin{center}
\includegraphics[width=0.7\columnwidth]{shifter.png}
%TODO last update : 24/05
\end{center}
\section{MEM}
\texttt{MEM} only make requests to memory if required and produces two results to \texttt{WB} : the output of \texttt{EXE} and the result from memory.
Output bits are on register.
\section{WB}
\texttt{WB} writes back values to the register. If the instructions are a memory load, this stage also does the following (since all load requests are a request to memory to load a word).
\begin{itemize}
......@@ -201,6 +196,36 @@ As example this a logical shift left with a 4 bits input and a 2 bit shift amoun
\item Extend or not the bit sign in case of a \texttt{LH} or \texttt{LB}
\end{itemize}
\section{Scanpath}
It's possible to insert scanpath, after synthesis. Scanpath can write and read value for register of r5, it is use to specify a state for debugging. Note that we dont put register from 32 general purpose register inside our scanpath, so contents is undefined and must be speficy by multiple insert of scan vector. When r5 is on mode test (for scan vector insertion/output) no write or invalidation can be made to general purpose register. Also note that scan vector values dependent of synthesis result, so scan vector for synthesis with yosys is not compatible with scan vector for synthesis with Alliance (mostly because FSM state arent encode in the same way). \\
Content of scanpath (\texttt{riscv\_core[Yosys/Alliance]\_scanpath.py}:
\begin{itemize}
\item \texttt{dec} :
\begin{itemize}
\item \texttt{pushed\_to\_exe}
\item \texttt{cur\_state} 0-1
\item \texttt{next\_pc(0)}
\item \texttt{bypass\_rd\_when\_exe\_valid}
\item \texttt{bypass\_rd\_when\_exe(0)} 0-4
\item \texttt{bypass\_rd\_on\_dec\_valid}
\item \texttt{bypass\_rd\_on\_dec(0)} 0-4
\end{itemize}
\item Fifo content of \texttt{fifo\_dec\_to\_exe} 0-115
\item Fifo validity of \texttt{fifo\_dec\_to\_exe}
\item Fifo content of \texttt{fifo\_dec\_to\_ifetch} 0-31
\item Fifo validity of \texttt{fifo\_dec\_to\_ifetch}
\item Fifo content of \texttt{fifo\_exe\_to\_mem} 0-79
\item Fifo validity of \texttt{fifo\_exe\_to\_mem}
\item Fifo content of \texttt{fifo\_ifetch\_to\_dec} 0-63
\item Fifo validity of \texttt{fifo\_ifetch\_to\_dec}
\item Fifo content of \texttt{fifo\_mem\_to\_wb} 0-73
\item Fifo validity of \texttt{fifo\_mem\_to\_wb}
\end{itemize}
\newpage
\section*{Bibliography}
\addcontentsline{toc}{section}{Bibliography}
......
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