Commit ff72d39e authored by Vrignault's avatar Vrignault

Fabrication AR

parent 3a7a4a86
......@@ -4,13 +4,18 @@ ActiveRecorder
=
**Active Recorder** est un enregistreur actif permettant d'écouter en hétérodyne et d'enregistrer des fichiers wav jusqu'à 500kHz de fréquence d'échantillonnage (384kHz en standard). La fonction hétérodyne fonctionne en manuel (comme un hétérodyne classique) ou en automatique (réglage automatique en fonction de la FME détectée et ajustement manuel +/-10kHz). Une fonction d'écoute en différé permet d'écouter les fichiers enregistrés en expansion de temps X10 ou en hétérodyne manuel. Il propose aussi les mêmes fonctionnalités que Passive Recorder (enregistrements en automatique, test micro, protocoles vigie chiro).
Les prototypes fonctionnent. Il utilise le même logiciel que Passive Recorder.
Le dossier de fabrication est réduit au minimum en attendant une solution pour la boite en plastique...
Les prototypes fonctionnent. Ils utilisent le même logiciel que Passive Recorder.
Le dossier de fabrication est quasi complet avec une carte électronique pré-montée qu'il est possible de commander chez JLCPCB. Cette solution permet de garder un prix très bas (<130€) et simplifie grandement le montage avec aucune soudure délicate.
Pour la boite, une opération de financement participatif est en cours pour les 100 premières [sur ce lien](https://www.helloasso.com/associations/association%20centre%20social%20du%20chemillois/collectes/active-recorder-pour-chauves-souris-financement-participatif-de-la-boite). C'est la seule solution pour se procurer une boite.
ActiveRecorder
=
**Active Recorder** is an active recorder for listening in heterodyne and recording wav files up to 500kHz sample rate (384kHz as standard). The heterodyne function works in manual (like a classic heterodyne) or in automatic (automatic adjustment according to the FME detected and manual adjustment +/- 10kHz). A delayed listening function allows you to listen to the recorded files in time expansion X10 or in manual heterodyne. It also offers the same features as Passive Recorder (automatic recordings, micro test, protocols vigie chiro).
The prototypes work. It uses the same software as Passive Recorder.
The manufacturing file is reduced to a minimum while waiting for a solution for the plastic box...
The prototypes work. They use the same software as Passive Recorder.
The manufacturing file is almost complete with a pre-assembled electronic card that can be ordered from JLCPCB. This solution makes it possible to keep a very low price (<130 €) and greatly simplifies the assembly with no delicate welding.
For the box, a crowdfunding operation is underway for the first 100 [on this link](https://www.helloasso.com/associations/association%20centre%20social%20du%20chemillois/collectes/active-recorder-pour-chauves-souris-financement-participatif-de-la-boite). It's the only way to get a box.
![PCB pré-montée](https://git.framasoft.org/PiBatRecorderPojects/TeensyRecorders/raw/master/Photos/PCB-AR.JPG)
![AR assemblé](https://git.framasoft.org/PiBatRecorderPojects/TeensyRecorders/raw/master/Photos/PCBCompletAR.JPG)
\ No newline at end of file
This diff is collapsed.
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update=22/05/2015 07:44:53
update=18/10/2019 09:36:28
version=1
last_client=kicad
last_client=pcbnew
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
......@@ -31,3 +12,238 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.3
ViaDiameter1=0.6
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.2
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.2
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1
TrackWidth=0.3
ViaDiameter=0.6
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Large
Clearance=0.1
TrackWidth=0.3
ViaDiameter=0.6
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
......@@ -11,7 +11,7 @@
(via_costs 50)
(plane_via_costs 5)
(start_ripup_costs 100)
(start_pass_no 2469)
(start_pass_no 5510)
(layer_rule F.Cu
(active on)
(preferred_direction horizontal)
......@@ -27,9 +27,9 @@
)
(rule
(width 300.0)
(clear 200.2)
(clear 100.2)
(clear 150.0 (type smd_to_turn_gap))
(clear 50.0 (type smd_smd))
(clear 25.0 (type smd_smd))
)
(padstack "Via[0-1]_600:400_um"
(shape
......@@ -69,10 +69,17 @@
)
)
(class "kicad_default"
"Net-(C1-Pad1)" "Net-(C1-Pad2)" "Net-(C2-Pad1)" "Net-(C4-Pad1)" "Net-(C4-Pad2)" "Net-(C5-Pad1)" "/SDA_E" "/SCL_E"
"Net-(R3-Pad1)" "Net-(R5-Pad1)" "Net-(R5-Pad2)" "Net-(R6-Pad2)" "Net-(R7-Pad2)" "/Mesure_Batteries" SAUDIO "/Mesure_Heterodyne"
/Up /Rec /Down /Push /Mode "/Sortie_Audio" "Net-(J6-Pad2)" "Net-(J5-Pad4)"
"Net-(J5-Pad5)" "Net-(U1-Pad25)" /D+ "/D-"
"Net-(C1-Pad1)" "Net-(C1-Pad2)" "Net-(C2-Pad1)" "Net-(C4-Pad1)" "Net-(C5-Pad1)" "/SDA_E" "/SCL_E" "Net-(R5-Pad2)"
"Net-(R6-Pad2)" "Net-(R7-Pad2)" "/Mesure_Batteries" SAUDIO "/Mesure_Heterodyne" /Up /Rec /Down
/Push /Mode "Net-(C13-Pad2)" "Net-(C13-Pad1)" "/Sortie_Audio" "Net-(J5-Pad4)" "Net-(U1-Pad25)" /D+
"/D-" "Net-(C17-Pad2)" "Net-(C18-Pad2)" "Net-(D1-Pad1)" "Net-(D3-Pad1)" "Net-(R18-Pad2)" "Net-(R20-Pad2)" "Net-(R21-Pad1)"
"Net-(R22-Pad1)" "Net-(C21-Pad2)" "Net-(C21-Pad1)" "Net-(C22-Pad1)" "Net-(J2-Pad4)" "Net-(U1-Pad17)" "Net-(U1-Pad18)" "Net-(U1-Pad19)"
"Net-(U1-Pad20)" "Net-(U1-Pad16)" "Net-(U1-Pad15)" "Net-(U1-Pad14)" "Net-(U1-Pad21)" "Net-(U1-Pad22)" "Net-(U1-Pad23)" "Net-(U1-Pad24)"
"Net-(U1-Pad30)" "Net-(U1-Pad31)" "Net-(U1-Pad32)" "Net-(U1-Pad33)" "Net-(U1-Pad35)" "Net-(U1-Pad13)" "Net-(U1-Pad12)" "Net-(U1-Pad11)"
"Net-(U1-Pad7)" "Net-(U1-Pad6)" "Net-(U1-Pad3)" "Net-(U1-Pad2)" "Net-(U1-Pad38)" "Net-(U1-Pad40)" "Net-(U1-Pad41)" "Net-(U1-Pad47)"
"Net-(U1-Pad48)" "Net-(U1-Pad49)" "Net-(U1-Pad50)" "Net-(U9-Pad4)" "Net-(U10-Pad4)" "Net-(R23-Pad2)" "Net-(D4-Pad1)" "Net-(U12-Pad4)"
"Net-(U12-Pad5)" "Net-(U10-Pad1)" "Net-(U10-Pad3)" "Net-(C15-Pad2)" "Net-(U12-Pad2)" "Net-(U13-Pad5)" "Net-(C14-Pad2)" "Net-(J6-Pad4)"
"Net-(J6-Pad3)" "Net-(J9-Pad2)" "Net-(C19-Pad2)" "Net-(R25-Pad1)" "Net-(C14-Pad1)"
(clearance_class "kicad_default")
(via_rule kicad_default)
(rule
......@@ -83,12 +90,12 @@
)
)
(class Large
GND +3V3 "+3V7_Permanent" AGND +5V "/+3V7_D" "/+3V7_C" "/+5V_C"
/+BAT1 "/-BAT1" /+BAT2 "/-BAT2"
GND +3V3 AGND +5V "/+3V7_C" "-BAT1" "-BAT2" VUSB
+BAT1
(clearance_class Large)
(via_rule Large)
(rule
(width 800.0)
(width 300.0)
)
(circuit
(use_layer F.Cu B.Cu)
......
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
update=22/05/2015 07:44:53
update=19/10/2019 16:06:44
version=1
last_client=kicad
last_client=pcbnew
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
......@@ -31,3 +12,238 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.3
ViaDiameter1=0.6
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.2
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.2
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.3
TrackWidth=0.3
ViaDiameter=0.6
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Large
Clearance=0.3
TrackWidth=0.3
ViaDiameter=0.6
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
......@@ -11,7 +11,7 @@
(via_costs 50)
(plane_via_costs 5)
(start_ripup_costs 100)
(start_pass_no 325)
(start_pass_no 138)
(layer_rule F.Cu
(active on)
(preferred_direction horizontal)
......@@ -69,8 +69,7 @@
)
)
(class "kicad_default"
"Net-(C13-Pad2)" "Net-(C13-Pad1)" "Net-(C14-Pad1)" "Net-(C15-Pad1)" "Net-(C15-Pad2)" "Net-(J7-Pad2)" "Net-(J7-Pad1)" "Net-(J8-Pad2)"
"Net-(J8-Pad3)" "Net-(R16-Pad2)" HPA "Net-(J7-Pad3)" HPB "Net-(C16-Pad1)"
"Net-(J7-Pad2)" "Net-(J7-Pad1)" "Net-(J8-Pad2)" "Net-(J8-Pad3)" "Net-(J7-Pad3)" "Net-(J7-Pad4)" "Net-(J8-Pad4)" "Net-(J8-Pad1)"
(clearance_class "kicad_default")
(via_rule kicad_default)
(rule
......
This diff is collapsed.
......@@ -40,46 +40,87 @@ X -3V7B 4 -250 -150 100 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Alimentations_Chargeur5V>4V2-eletechsup
# Alimentations_DMG9926USD
#
DEF ~Alimentations_Chargeur5V>4V2-eletechsup U 0 40 Y Y 1 F N
F0 "U" -50 200 50 H V L CNN
F1 "Alimentations_Chargeur5V>4V2-eletechsup" -400 300 50 H I L CNN
F2 "" -200 -200 50 H I L CIN
F3 "" 0 0 50 H I L CNN
$FPLIST
DIP*W7.62mm*
$ENDFPLIST
DEF Alimentations_DMG9926USD U 0 40 Y Y 1 F N
F0 "U" 300 50 60 H V C CNN
F1 "Alimentations_DMG9926USD" 550 -50 60 H V C CNN
F2 "Housings_SOIC:SOIC-8_3.9x4.9mm_Pitch1.27mm" 50 -450 60 H I C CNN
F3 "" 232 2 60 H I C CNN
DRAW
T 0 200 -100 40 0 0 0 +4V2 Normal 0 C C
T 0 -200 -100 40 0 0 0 +5V Normal 0 C C
T 0 200 -50 40 0 0 0 BAT Normal 0 C C